1. Field of the Invention
This disclosure relates to a method of fabricating a semiconductor device, and more particularly a method of forming a self-aligned contact structure using a sacrificial mask layer.
2. Description of the Related Art
As integrated circuit devices become more highly integrated, the width of interconnections and spacing between interconnections have also been reduced. Self-aligned contact technology has been used to increase alignment margins when using a photolithography technique to form contact holes in predetermined regions between the interconnections.
FIG. 1A to FIG. 1E are cross-sectional diagrams illustrating a method of forming a self-aligned contact structure in accordance with a conventional technique.
Referring to FIG. 1A, a lower insulating layer 20 is formed on a semiconductor substrate 10. Next, a lower conductive layer 30 and a mask layer 40 are sequentially formed on the entire surface of the semiconductor substrate 10 having the lower insulating layer 20 thereon. The mask layer 40 is typically formed of a silicon nitride layer.
Referring to FIG. 1B, the mask layer 40 and the lower conductive layer 30 of FIG. 1A are sequentially patterned to form interconnection patterns 37 having interconnections 35 and mask patterns 45 stacked in sequence. A silicon nitride layer is then formed on the entire surface of the semiconductor substrate having the interconnection patterns 37. An etching back process is performed against the entire surface of the semiconductor substrate having the silicon nitride layer, so that spacers 50 are formed on sidewalls of the interconnection patterns 37.
Referring to FIG. 1C, an interlayer insulating layer 60 is formed on the entire surface of the semiconductor substrate having the interconnection patterns 37 and spacers 50. The interlayer insulating layer 60 completely fills gap regions between the interconnection patterns 37. The interlayer insulating layer 60 is formed of silicon oxide.
Referring to FIG. 1D, a photo-resist pattern 70 having openings, through which the interlayer insulating layer 60 is selectively exposed, is formed on the interlayer insulating layer 60 to form contact holes. The interconnection patterns 37 and the spacers 50 may be partially located under the openings. The interlayer insulating layer 60 is etched using the photo-resist pattern 70 as an etching mask. The interconnection patterns 37 and the spacers 50 located under the openings may serve as etching masks too, so that self-aligned contact holes 75 exposing predetermined regions of the semiconductor substrate 10 are formed.
During the etching process of the interlayer insulating layer 60 a large amount of upper portions of the mask patterns 45 of the interconnection patterns 37 and the spacers 50 is etched away because the mask patterns 45 and the spacers 50 are formed of a silicon nitride layer. Accordingly, upper corners of the interconnections 35 become close to the contact holes 75, or the interconnections 35 may even be exposed through the contact holes 75.
Referring to FIG. 1E, the photo-resist pattern 70 of FIG. 1D is stripped off after the contact holes 75 are formed. An upper conductive layer is formed on the entire surface of the semiconductor substrate 10 to completely fill the contact holes 75. The upper conductive layer is planarized until the upper surface of the interlayer insulating layer 60 is exposed. As a result, a number of contact plugs 85 isolated by the interlayer insulting layer 60 are formed in the contact holes 75.
The conventional technique described above is advantageous in that it is possible to lower an aspect ratio of a contact hole to be formed on the pad plugs by forming such pad plugs 85 in advance, and it has good process margins because self-aligned contact holes are formed.
However, the conventional technique described above has disadvantages as well, as described below.
First, as described referring to FIG. 1D, upper corners of the interconnections 35 may be exposed through the contact holes 75 because the mask patterns 45 and the spacers 50 are partially etched away when the self-aligned contact holes 75 are formed. The exposed interconnections 35 short with the plugs 85, and may cause a device failure. Even if the interconnections 35 are not exposed through the contact holes 75, since the interconnections 35 and the contact holes 75 are too close, a breakdown voltage is low and a device failure may be caused.
Second, in the case of increasing a thickness of the mask layer 40 (FIG. 1A) to prevent the shorts between the interconnections 35 and the plugs 85, a photo lithography process and an etching process to form the mask patterns 45 are difficult and complicated. Further, in such cases, aspect ratios of the contact holes 75 increase, and the fabricated semiconductor device is structurally weak because the increased total height of the device.
Third, in accordance with the conventional technique, as described referring to FIG. 1B, the spacers 50 are formed by forming the silicon nitride layer on the entire surface of the semiconductor substrate 10 having the interconnection patterns 37, and etching back the entire surface of the silicon nitride layer. Accordingly, the spacers 50 cover the sidewalls of the interconnection patterns 37. After filling the remaining space with the interlayer insulating layer 60, dielectric films that include a spacer 50, the interlayer insulating layer 60 and another spacer 50 are interposed between the interconnections 35 as shown in FIG. 1C. In this case, since a silicon nitride layer forming the spacers 50 has a greater dielectric constant than a silicon oxide layer forming the interlayer insulating layer 60, a coupling capacitance between the interconnections 35 is large.
Embodiments of the invention address these and other disadvantages of the prior art.